The present invention relates to a semiconductor device and a manufacturing method thereof, and particularly to a highly integrated semiconductor device having a capacitor with high reliability and large capacitance, and a method for manufacturing the same. The present invention relates to the present inventor's co-pending U.S. patent application Ser. No. 07/715,913, now U.S. Pat. No. 5,274,258 filed on Jun. 14, 1991.
Decrease in cell capacitance caused by reduced memory cell area becomes a serious obstruction to the increase of packing density in dynamic random access memories (DRAMs). Thus, the problem of decreased cell capacitance must be solved so as to achieve higher packing density in a semiconductor memory device, since it degrades read-out capability and increases the soft error rate of a memory cell as well as consumes excessive power during low-voltage operation by impeding device operation.
Generally, in a 64 Mbit DRAM having a 1.5 .mu.m.sup.2 memory cell area, when employing a two-dimensional stacked structure memory cell, sufficient cell capacitance cannot be obtained even though a higher dielectric constant material, e.g., tantalum oxide (Ta.sub.2 O.sub.5) is used. Therefore, stacked capacitors having a three-dimensional structure have been suggested to improve cell capacitance. The double stack, fin, cylindrical electrode, spread stack, and box structures are all for a storage electrode having a three-dimensional structure proposed to increase cell capacitance.
Since both outer and inner surfaces can be utilized as an effective capacitor area, the cylindrical structure is favorably adopted to the three-dimensional stacked capacitor, and suitable for an integrated memory cell which is 64 Mb or higher. Also, an improved stacked capacitor with a ring structure has recently been presented, wherein a bar is formed in the interior of the cylinder, thereby utilizing not only both inner and outer surfaces of the cylinder but also the outer surface of the bar formed in the interior of the cylinder as the effective capacitor area ("A Stacked Capacitor Cell with Ring Structure," 22nd Conference on SSDN 1990, Part II, pp. 833-836).
FIGS. 1A through 1G are sectional views illustrating a process for forming a cylindrical storage electrode having a bar electrode therein.
An insulating inter layer 19 and a nitride layer 22 are sequentially stacked on a semiconductor substrate wherein a transistor having a source 14, a drain 16 and a gate electrode 18, and a buried bit line 20 in contact with the drain region of the transistor, have been formed (FIG. 1A). Then, the insulating inter-layer and nitride layer deposited on the source region are partially etched, thereby forming a contact hole 24 (FIG. 1B). Successively, a first polycrystalline silicon layer 26 having a predetermined thickness is formed on nitride layer 22, filling contact hole 24, and an oxide layer is stacked thereon and patterned to form a bar electrode within a cylinder, thereby forming an oxide layer pattern 28 (FIG. 1C). Thereafter, a predetermined depth of first polycrystalline silicon layer 26 is etched-back, using oxide layer pattern 28, so that a bar electrode 26a is formed, and an insulating layer with an etch selectivity different from that of oxide layer pattern 28 is formed on the first polycrystalline silicon layer. Then, the insulating layer is removed by an anisotropic etching. Here, portions of the insulating layer remain on the sidewalls of oxide layer pattern 28 and bar electrode 26a, thereby forming a spacer 30 (FIG. 1D). After coating a second polycrystalline silicon layer on the whole surface of the semiconductor substrate whereon oxide layer pattern 28, spacer 30, and bar electrode 26a are formed, the first and second polycrystalline silicon layers are anisotropically etched to form other spacers composed of the second polycrystalline silicon on the side of spacer 30, completing a cylindrical electrode 32 (FIG. 1E). Also, oxide layer pattern 28 and spacer 30 are removed by a wet etching, so that storage electrodes S1 and S2 formed of bar electrode 26b and cylindrical electrode 32 are completed (FIG. 1F).
Finally, a dielectric layer 34 is covered on the whole surface of the storage electrode, a third polycrystalline silicon is deposited on the whole surface of the semiconductor substrate, completing a stacked capacitor with a ring structure (FIG. 1G).
The above-described highly integrated semiconductor memory device has been adopted as a leading model which realizes 64 Mbit DRAM cells. That is because, a bar electrode is formed within the cylindrical electrode, so that the inner and outer surfaces of the cylindrical electrode as well as the outer surface of the bar electrode can be utilized as an effective capacitor region. However, the above memory device formed of the cylindrical and bar electrodes has a problem in that the cylindrical and bar electrodes are formed by different layers of a conductive material (not a single layer), which creates inconvenience in manufacturing. Besides, the cylindrical electrode is formed by an anisotropic etching of the second polycrystalline silicon layer, thereby forming double spacers on the sidewall of spacer 30, wherein the etched amount of the second polycrystalline silicon layer is inconsistent throughout the wafer, so that the height of cylindrical electrode 32 varies between its periphery and center, which can result in cells of different capacitances, even on the same wafer. Generally, if an etched object is a polycrystalline silicon, a storage electrode in the center of the wafer can be formed as shown the section view of FIG. 1H since the etch rates are different from each other in the periphery and center. Therefore, the obtained cell capacitance may be lower than the desired cell capacitance. In addition, due to forming cylindrical electrode 32 by an additional spacer on the sidewall of spacer 30, the top of the cylindrical electrode becomes sharp due to the double anisotropic etching, which is likely to cause breakdown of the dielectric layer coated thereon, and thus degrades the electrical characteristics, yield, and reliability of the device.